`timescale 1ns / 1ps
 
//顶层文件 输入两个数 选择（进位）
 
//输出两个 结果 进位
 
module ADDSUB_32(X, Y, Sub, S, Cout);// 32位加法器ADDSUB_32
 
    //sub 0是加法 1是减法
 
    input [31:0] X;
 
    input [31:0] Y;
 
    input Sub;
 
    output [31:0] S;
 
    output Cout;//输出进位信息
 
    //对输入的sub进行扩展 如果是加法的话0的话异或还是原数
 
    //如果是减的话做异或并且让进位信号为1
 
    CLA_32 add0 (X, Y^{32{Sub}}, Sub, S, Cout); 
 
endmodule
 
 
 
module CLA_32(X, Y, Cin, S, Cout);
 
    input [31:0] X, Y;
 
    input Cin;//输入进位信息
 
    output [31:0] S;
 
    output Cout;
 
    //32位分成8个CLA
 
    wire Cout0, Cout1, Cout2, Cout3, Cout4, Cout5, Cout6;
 
 
 
    CLA_4 add0 (X[3:0], Y[3:0], Cin, S[3:0], Cout0);
 
    CLA_4 add1 (X[7:4], Y[7:4], Cout0, S[7:4], Cout1);
 
    CLA_4 add2 (X[11:8], Y[11:8], Cout1, S[11:8], Cout2);
 
    CLA_4 add3 (X[15:12], Y[15:12], Cout2, S[15:12], Cout3);
 
    CLA_4 add4 (X[19:16], Y[19:16], Cout3, S[19:16], Cout4);
 
    CLA_4 add5 (X[23:20], Y[23:20], Cout4, S[23:20], Cout5);
 
    CLA_4 add6 (X[27:24], Y[27:24], Cout5, S[27:24], Cout6);
 
    CLA_4 add7 (X[31:28], Y[31:28], Cout6, S[31:28], Cout);
 
endmodule
 
 
 
module CLA_4(X,Y,Cin,S,Cout);
 
    input [3:0]X,Y;
 
    input Cin;
 
    output [3:0]S;
 
    output Cout;
 
    wire cout0,cout1,cout2,cout3;
 
    assign cout0=X[0]&Y[0]|((X[0]|Y[0])&Cin);
 
    assign cout1=X[1]&Y[1]|((X[1]|Y[1])&cout0);
 
    assign cout2=X[2]&Y[2]|((X[2]|Y[2])&cout1);
 
    assign Cout=X[3]&Y[3]|((X[3]|Y[3])&cout2);
 
    assign S[0]=X[0]^Y[0]^Cin;
 
    assign S[1]=X[1]^Y[1]^cout0;
 
    assign S[2]=X[2]^Y[2]^cout1;
 
    assign S[3]=X[3]^Y[3]^cout2;
 
endmodule